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RT8130C ? ds8130c-00 april 2016 www.richtek.com 1 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. 12v green voltage mode high efficiency synchronous buck pwm controller features ? ? ? ? ? green voltage mode (gvm tm ) control ? ? ? ? ? high light load efficiency ? ? ? ? ? single 5v to 12v driver voltage ? ? ? ? ? integrated high driving capability n-mosfet gate drivers ? ? ? ? ? 300khz fixed frequency internal oscillator ? ? ? ? ? 88% maximum pwm duty cycle ? ? ? ? ? power good indicator ? ? ? ? ? enable/disable control ? ? ? ? ? adaptive zero-current detection ? ? ? ? ? internal soft-start ? ? ? ? ? lossless low-side mosfet r ds(on) current sensing for over-current fault monitoring ? ? ? ? ? lgate over-current setting (lgocs) ? ? ? ? ? ocp, uvp, ovp, otp, uvlo applications ? motherboard, memory/chip-set power ? graphic card, gpu/memory core power ? low voltage, high current dc/dc regulator general description the RT8130C is a high efficiency single phase synchronous buck dc/dc controller with 5v/12v supply voltage. the ic features green voltage mode (gvm tm ) control, which is specifically designed to improve converter efficiency at light load condition. at light load condition, the ic automatically operates in the diode emulation mode with constant on-time pfm to reduce switching frequency so as to improve conversion efficiency. as the load current increases, the RT8130C leaves the diode emulation mode (dem) and operates in the continuous conduction mode with fixed frequency pwm. the RT8130C has embedded mosfet gate driver with high driving capability, supporting driving voltage up to 12v for high output current application. this device uses lossless low-side mosfet r ds(on) current sense technique for over-current protection with adjustable threshold set by the lgate pin (lgocs). other features include power good indication, enable/disable control and internal soft-start. the RT8130C also provides fault protection functions to protect the power stage output. with above functions, the ic provides customers a cost- effective solution for high efficiency power conversion. the RT8130C is available in the wdfn-10l 3x3 package. simplified application circuit v c c e n c o m p / e n u g a t e f b r t 8 1 3 0 c l g a t e b o o t p h a s e v i n p g o o d g n d v o u t v c c v p g o o d
2 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wdfn-10l 3x3 9 8 7 1 2 3 4 5 10 6 gnd 11 boot phase gnd lgate ugate pgood nc fb vcc comp/en kc= : product code ymdnn : date code marking information pin no. pin name pin function 1 boot bootstrap supply for high-side gate driver. connect this pin to a power source v cc through a bootstrap diode, and connect a 0.1 ? f or greater ceramic capacitor from this pin to the phase pin to supply the power for high-side gate driver. 2 phase switch node. connect this pin to the switching node of buck converter. this pin is also the floating drive return of the high-side mosfet gate driver. the phase voltage is sensed for zero current detection and over-current protection when low-side mosfet is on. 3 ugate high-side mosfet gate driver output. connect this pin to the gate of high- side mosfet for floating drive. 4 lgate low-side mosfet gate driver output. connect this pin to the gate of low-side mosfet. this pin is also used for over-current protection (ocp) threshold setting. connect a resistor (r ocset ) from this pin to the gnd pin to set the ocp threshold. 5, 11 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 6 vcc supply voltage input. it is recommended to connect a 1 ? f or greater ceramic capacitor from this pin to the gnd pin. vcc also powers the low-side gate driver. 7 comp/en compensation node. connect r-c network between this pin and the fb pin for pwm control loop compensation. this pin is also used for enable/disable control. connect a small signal mosfet to this pin to implement enable/disable control. 8 fb feedback voltage input. this pin is used for output voltage feedback input and it is also monitored for power good indication, over-voltage and under-voltage protections. connect this pin to the converter output through voltage divider resistors for output voltage regulation. 9 nc no internal connection. 10 pgood power good indicator output. this pin provides an open-drain output. connect this pin to a voltage source through a pull-up resistor. the pgood voltage goes high to indicate the output voltage is in regulation. this pin can be left open if the power good indication function is not used. RT8130C package type qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free) kc=ym dnn
3 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram operation the RT8130C is a high efficiency single-phase green voltage mode (gvm tm ) synchronous buck controller with integrated mosfet driver. the controller has a fixed frequency control, a fixed frequency 300khz oscillator is integrated to minimize external components. enable the RT8130C remains in shutdown if the comp/en pin is lower than 0.3v (max). when the comp/en pin rises above the enable trip point, the RT8130C will begin a soft- start cycle. over-current threshold setting current limit threshold is externally programmed by adding a resistor (r ocset ) between lgate and gnd. once vcc exceeds the por threshold, an internal current source i oc flows through r ocset . the voltage across r ocset is stored as the current limit protection threshold. after that, the current source is switched off. under-voltage protection if the fb voltage is lower than the uvp threshold during normal operation, uvp will be triggered. when the uvp is triggered, both ugate and lgate go low until vcc is resupplied and exceeds the por rising threshold voltage. over-voltage protection if the fb pin voltage is higher than the ovp threshold during normal operation, ovp will be triggered. when ovp is triggered, ugate will go low and lgate will go high until vcc is resupplied and exceeds the por rising threshold voltage. + - - + + - - + uv ov uv_level ov_level pgh_level pgl_level comp/en + - cmp pwm + - cmp v ref - + ea v ref pgood fb current sense & ocp comparator -1 lgate gnd v cc i ocset v cc boot ugate phase control logic regulator vcc oc
4 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v cc = 12v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) ? supply voltage, vcc --------------------------------------------------------------------------------------------- 15v ? boot to phase -------------------------------------------------------------------------------------------------- 15v ? pgood -------------------------------------------------------------------------------------------------------------- 15v ? input, output or i/o voltage ------------------------------------------------------------------------------------- gnd ? 0.3v to 7v ? phase to gnd (note 2) dc --------------------------------------------------------------------------------------------------------------------- ? 5v to 30v < 20ns --------------------------------------------------------------------------------------------------------------- ? 10v to 30v ? ugate to phase dc --------------------------------------------------------------------------------------------------------------------- ? 0.3v to (v boot + 0.3v) < 20ns --------------------------------------------------------------------------------------------------------------- ? 5v to (v boot + 5v) ? lgate to gnd dc --------------------------------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) < 20ns --------------------------------------------------------------------------------------------------------------- ? 5v to (v cc + 5v) ? power dissipation, p d @ t a = 25 c (note 3) wdfn-10l 3x3 ----------------------------------------------------------------------------------------------------- 3.27w ? package thermal resistance wdfn-10l 3x3, ja ----------------------------------------------------------------------------------------------- 30.5 c/w wdfn-10l 3x3, jc ----------------------------------------------------------------------------------------------- 7.5 c/w ? junction temperature --------------------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 sec.) ------------------ ----------------------------------------------------- 260 c ? storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c ? esd susceptibility (note 4) hbm (human body model) -------------------------------------------------------------------------------------- 2kv recommended operating conditions (note 5) ? power input voltage, vi n ---------------------------------------------------------------------------------------- 2.5v to 21v ? supply input voltage, vcc -------------------------------------------------------------------------------------- 4.5v to 13.2v ? junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c ? ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c parameter symbol test conditions min typ max unit general supply input voltage v cc 4.5 12 13.2 v vcc supply current i cc no load for ugate/ lgate -- 2 -- ma vcc por threshold v porh v cc rising -- 4.1 4.2 v v rorl v cc falling 3.6 3.8 -- vcc por hysteresis -- 0.3 -- v soft-start interval t ss v fb from 0v to 0.8v 3 -- 7 ms reference voltage v ref 0.793 0.8 0.807 v
5 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. (phase to gnd + vcc) should not higher than 43.2v. note 3. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 4. devices are esd sensitive. handling precaution is recommended. note 5. the device is not guaranteed to function outside its operating conditions. note 6. guaranteed by design. parameter symbol test conditions min typ max unit protection thermal shutdown limit t sd -- 165 -- ? c over-voltage threshold v ovp relative to fb voltage 115 125 135 % under-voltage threshold v uvp relative to fb voltage -- 75 -- % oc current source i oc 9 10 11 ? a oc preset trigger voltage v oc_preset r ocset is not populated -- 0.6 -- v over current setting time delay t ocp from v cc > 4.5v to soft-start -- -- 5 ms mosfet gate driver ugate drive source i ugatesr v boot ? v phase = 12v, max source current -- 1.5 -- a lgate drive source i lgatesr v lgate = 12v, max source current -- 1.5 -- a ugate drive sink r ugatesk v ugate ? v phase = 0.1v -- 1.8 -- ? lgate drive sink r lgatesk v lgate = 0.1v -- 1.2 -- ? dead time t dead -- 30 -- ns pwm controller ea open loop gain g ea (note 6) -- 80 -- db ea bandwidth bw (note 6) -- 15 -- mhz maximum duty d max -- 88 -- % ramp valley -- 0.9 -- v ramp amplitude ? v osc v in = 12v -- 1.6 -- v comp/en disable threshold -- -- 0.3 v pwm frequency f osc 270 300 330 khz zero crossing threshold (note 6) ? 10 -- 0 mv pgood threshold v pgood_h relative to fb voltage 0.86 0.89 0.92 v v pgood_l relative to fb voltage 0.68 0.71 0.74 pgood low level v ol_pgood sink current = 4ma -- -- 0.4 v en to soft-start delay t delay_en (note 6) -- -- 500 ? s
6 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit v cc e n 7 3 2 4 8 c o m p / e n u g a t e f b r t 8 1 3 0 c l g a t e 1 b o o t p h a s e 1.2h v in p g o o d 1 0 g n d 5 , 1 1 ( e x p o s e d p a d ) 0 q 1 q 2 c o u t v o u t v c c 6 c boot 0 r ocset r fb1 r2 c2 r l 13.7k 82pf c s r s c b p c4 d boot v pgood 1 0 k c snb r snb 2 . 2 c 1 r 1 n c 2 . 2 f r p g o o d c p 8.2k 4.7nf r fb2 r boot r ugate 0.1f 10k 1 2.2nf 10f x 4 470f x 2 2.5v to 21v l1 4.3k 8.2nf 560 820f x 2 up to 12v 5v to 12v
7 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output voltage vs. output current 1.093 1.094 1.095 1.096 1.097 1.098 1.099 1.100 1.101 1.102 1.103 0 5 10 15 20 25 30 output current (a) output voltage (v) v in = v cc =12v, v out = 1.1v reference voltage vs. temperature 0.794 0.795 0.796 0.797 0.798 0.799 0.800 0.801 0.802 0.803 0.804 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = v cc =12v, no load efficiency vs. output current 60 65 70 75 80 85 90 0 3 6 9 12 15 18 21 24 27 30 output current (a) efficiency (%) v in = v cc =12v, v out = 1.1v, i out = 0a to 30a, l = 1 h, dcr = 1.7m power off from v cc time (4ms/div) v in = v cc =12v, v out = 1.1v, i load = 10a v cc (10v/div) ugate (50v/div) v out (1v/div) lgate (10v/div) power on from v cc v in = v cc =12v, v out = 1.1v, i load = 10a time (4ms/div) v cc (10v/div) ugate (50v/div) v out (1v/div) lgate (10v/div) efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 output current (a) efficiency (%) v in = v cc =12v, v out = 1.1v, i out = 0.01a to 10a, l = 1 h, dcr = 1.7m
8 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ovp time (200 s/div) v in = v cc =12v, v out = 1.1v, no load v fb (1v/div) ugate (20v/div) pgood (10v/div) lgate (20v/div) uvp time (2ms/div) v in = v cc =12v, v out = 1.1v, no load v fb (1v/div) ugate (20v/div) pgood (10v/div) lgate (20v/div) short ocp time (5 s/div) v in = v cc =12v, v out = 1.1v, r ocset = 7.5k inductor current (20a/div) ugate (20v/div) pgood (20v/div) lgate (20v/div) power off from comp/en time (400 s/div) v in = v cc =12v, v out = 1.1v, i load = 10a comp/en (2v/div) ugate (20v/div) v out (1v/div) lgate (10v/div) ocp time (5 s/div) v in = v cc =12v, v out = 1.1v, r ocset = 7.5k inductor current (20a/div) ugate (20v/div) pgood (20v/div) lgate (20v/div) power on from comp/en time (2ms/div) v in = v cc =12v, v out = 1.1v, i load = 10a comp/en (2v/div) ugate (20v/div) v out (1v/div) lgate (10v/div)
9 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. load transient response time (100 s/div) v in = v cc =12v, v out = 1.1v, i load = 6a to 30a i load (20a/div) ugate (20v/div) v out (50mv/div) lgate (20v/div)
10 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 1. power up operation application information supply voltage and power-on reset the vcc pin is the power supply pin of the RT8130C. the input voltage range (v cc ) is from 4.5v to 13.2v with respect to the gnd pin. an internal linear regulator regulates the supply voltage for internal control logic circuit. the vcc pin also supplies the power for the integrated low-side mosfet gate driver. a 1 f ceramic capacitor or greater is recommended for the vcc voltage de-coupling. place the de-coupling capacitor physically close to the vcc pin. the power-on reset (por) circuit monitors the vcc pin voltage. if v cc exceeds the por rising threshold, the controller begins to work and prepares for soft-start operation. if v cc falls below the por falling threshold, the controller stops working. all mosfets stop switching, and all protections are reset. there is a hysteresis between the por rising and falling thresholds to prevent inadvertently reset caused by noise. soft-start when the controller input voltage (v cc ) rises and exceeds the por rising threshold at power up, the RT8130C initiates soft-start operation after the t ocp time delay. the soft-start function is used to prevent large inrush current from input power source while converter is powered up. the ic provides soft-start function internally. the fb voltage will track the internal soft-start voltage, which ramps up from zero in a monotone during the soft-start period. therefore, the duty cycle of pwm signal will increase gradually and so does the input current. figure 1 shows the power-up operation of RT8130C. the ic operates firstly in gvm during soft-start period ~3t ss . when the gvm period ends, the ic enters ultrasonic mode (usm) or ccm depending on the load current. green voltage mode (gvm) control the RT8130C utilizes gvm control to improve light load efficiency. depending on the load current, the controller automatically operates in diode emulation mode (dem) with constant on-time pfm or in continuous conduction mode (ccm) with fixed-frequency pwm. at light load condition, the ic automatically operates in diode emulation mode with constant on-time pfm to reduce switching frequency so as to improve efficiency. as the output current decreases from heavy load condition, the inductor current decreases, and eventually the inductor valley current decreases to zero, which is the boundary between continuous conduction mode and discontinuous conduction mode. by emulating the behavior of diodes, the low-side mosfet allows only partial of negative current to flow when the inductor freewheeling current reaches negative. as the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that next ugate on-time begins. the ugate on-time in dem is determined by the converter input and output voltage, and it is generated internally. when the output current increases from light load to heavy load, the v cc v out v cc por t ocp ultrasonic mode (usm) with diode emulation (variable frequency) /pwm (fixed 300khz) t ss t 2 x t ss (load current dependent) gvm ?
11 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. switching frequency increases to the value as the inductor current reaches the continuous conduction condition. controller will then operate in continuous conduction mode with 300khz fixed switching frequency pwm. the RT8130C activates ultrasonic mode operation with switching frequency higher than 25khz. the ultrasonic mode eliminates audio noise that would be presented when the controller automatically skips pulses at light load condition. in this mode, the low-side switch gate- driver signal is or with an internal oscillator. once the internal oscillator is triggered, the controller pulls lgate high, turning on the low-side mosfet to induce a negative inductor current. after v fb falls to v ref , the controller turns off the low-side mosfet (lgate pulled low) and triggers a constant on-time (ugate driven high). when the on-time is expired, the controller re-enables the low-side mosfet until the inductor current decreases below the zero crossing threshold. as the load current increases, the inductor current no longer reaches the zero-crossing threshold. the controller leaves the ultrasonic mode and enters the continuous conduction mode. in the continuous conduction mode, the controller operates with fixed switching frequency, and uses voltage mode pwm control for output voltage regulation. power up with pre-bias voltage conventionally, when the converter output capacitor has been pre-charged to a non-zero positive voltage, the fb pin voltage of the pwm controller is non-zero. if the converter is powered up under this condition, the soft- start function of pwm controller will turn on low-side mosfet with maximum duty ratio to rapidly discharge the output capacitor so as to force the fb voltage to track the internal soft-start voltage. large current is then drawn from the output capacitor while the discharge is taking place. the discharge current depends on the inductance and the output capacitance. output voltage may oscillate and go negative. the negative output voltage could damage the load. the RT8130C implements control circuits specifically to prevent the negative voltage when the converter is powered up with pre-biased voltage on the output capacitor. figure 2. power up with pre-biased output voltage enable/disable function the comp/en pin is used to enable or to disable the controller. because the comp/en pin is also the error amplifier output, it is recommended to use a small signal mosfet with low capacitance c gd to minimize the influence of the comp/en pin capacitance on loop response. use a small signal mosfet or bjt to implement the enable/disable control. connect the drain of small signal mosfet (or the collector of bjt) to the comp/en pin and its source (or the emitter of bjt) to ground for enable/disable control. if the comp/en voltage is pulled down below the enable level v en , the controller is disabled with both ugate and lgate go low after about 3 s delay time. if the comp/en pin is released, the comp/en voltage rises and then begins to soft-start. power good indication the RT8130C monitors the converter output voltage through the fb pin for power good indication, over-voltage protection and under voltage protection. the pgood pin is an open-drain output, and it should be tied to a voltage source v pgood no greater than 12v through a pull up resistor r pgood . referring to the typical application, it is recommended to choose the r pgood to set maximum 1ma sink current into the pgood pin. in order to prevent the high inrush current at power up beginning. the RT8130C control circuits specifically design the pre-biased power up circuit. and it only can be activated when v fb < 0.1v. figure 2 shows the waveform that converter is powered up with pre-biased output voltage. time (50ms/div) v out (5v/div) lgate (10v/div) ugate (20v/div) en (5v/div)
12 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ds(on) max ocset ocset ocset ocset ri v r ii ? ?? where i max represents the maximum inductor valley current, r ds(on) is the on state channel resistance of the low-side mosfet. if the r ocset is not connected, the internal current source i ocset will charge the c gs of the low-side mosfet during the ocp threshold setting period. under this condition, the lgate voltage may be high enough to turn on the low-side mosfet so that the output capacitor is discharged. although the lgate voltage may be high enough to turn on the low-side mosfet, the ocp threshold voltage is internally clamped at 600mv (typical) and stored as the preset value. if the fb pin voltage stays within the voltage window of 12% of v ref (typical), the pgood voltage will go high to indicate that the converter output voltage is in regulation. if the fb pin voltage is out of the voltage window, the pgood voltage goes low to indicate that the converter output voltage is out of regulation. if the power good indication function is not used, the pgood pin can be left open. over voltage protection (ovp) if the fb pin voltage is higher than the ovp threshold during normal operation, ovp will be triggered. when ovp is triggered, ugate will go low and lgate will go high to discharge the converter output capacitor to protect the load from over voltage condition. when the fb pin voltage falls below 0.1v, lgate will go low to stop the discharge. the ovp function belongs to a latch protection. the RT8130C will not repeat the soft-start operation unless the vcc voltage is toggled off and on to reset the ovp. under-voltage protection (uvp) if the fb pin voltage is lower than the uvp threshold during normal operation, uvp will be triggered. when uvp is triggered, both ugate and lgate will go low to protect the load from under-voltage condition. referring to figure 1, the uvp function is not activated until the soft-start period t ss completes. the uvp function belongs to a latch protection, and it is masked during the soft-start time t ss . the RT8130C will not repeat the soft-start operation unless the vcc voltage is toggled off and on to reset the uvp. a power on sequence should be concerned. when vcc exceeds than por threshold but vin is not present, the uvp will be triggered. so, the vin sequence should be earlier than vcc for successfully power up. over-current protection (ocp) the RT8130C utilizes low-side mosfet r ds(on) current sense technique for over-current protection (ocp). after low-side mosfet is turned on, the controller monitors the voltage across low-side mosfet by sensing the phase voltage. the RT8130C uses cycle-by-cycle inductor valley current sense, the controller samples and holds the phase voltage before low-side mosfet is turned off. this sampled phase voltage represents the inductor valley current, and it is compared with the user defined threshold voltage for ocp. when the inductor current exceeds the user defined threshold level for two consecutive pwm switching cycles, ocp will be triggered. when ocp is triggered, both ugate and lgate will go low to protect the load from over-current condition. the ocp function belongs to a latch protection. the ic will not repeat the soft-start operation unless the vcc voltage is toggled off and on to reset the ocp. lgate over-current protection threshold setting (lgocs) the lgate pin is not only for driving the low-side mosfet, but also is used to set the over-current protection (ocp) threshold. figure 3 shows the connection for ocp threshold setting, in which a resistor r ocset connected from the lgate pin to the gnd pin sets the ocp threshold. after the controller input voltage vcc exceeds the por rising threshold at power up, the ic waits for a period of time for ocp setting before soft-start operation begins. during this period, the ugate output is low and the lgate output is in tri-state. an internal current source i ocset is switched on and then flows out of the lgate pin to the external resistor r ocset to set the ocp threshold. the voltage drop across r ocset is stored by the controller as the ocp threshold v ocset . after that, the current source is switched off, and the lgate output leaves tri-state then goes low. the resistance value of r ocset is determined by the following equation :
13 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. ocp threshold setting bootstrap circuit figure 4 shows the bootstrap circuit, which is used for the high-side mosfet driving. the c boot is used to store and supply the energy for high-side mosfet floating drive, and the d boot is used for voltage blocking. choose the d boot with sufficient voltage rating to block the phase peak voltage (consider switching spike) plus the voltage v cc . when the low-side mosfet is on, the phase voltage is pulled down to ground and the d boot conducts to charge the c boot . when the high-side mosfet driver is on, part of the charge stored in the c boot is transferred to the high-side mosfet to turn it on. use 0.1 f or gre ater ceramic capacitor as the c boot to ensure the high-side mosfet gate driver operation. the c boot and d boot should be placed physically close to the boot and phase pins to minimize the trace parasitic components. figure 4. bootstrap circuit mosfet gate drivers in synchronous rectified buck topology, the dead-time is utilized to prevent cross conduction of high-side and low- side mosfets. the RT8130C implements non-overlapping mosfet gate drivers with dead-time control scheme to ensure a safe operation of mosfet switching. for high output current applications, multiple power mosfets are usually paralleled to reduce the total r ds(on) . the mosfet gate driver needs to have higher driving capability to switch on/off these paralleled mosfets. the RT8130C integrates mosfet gate drivers that have high current driving capability to have lower switching loss and thus better performance of conversion efficiency. the embedded mosfet drivers contribute to the majority of power dissipation of the controller. therefore, wdfn package is chosen because of its power dissipation rating. if gate resistor is not used, the power dissipation of the controller can be approximately calculated by the following equation : p sw = f sw (q g_high x v boot-phase + q g_low x v cc ) although the ocp threshold voltage is internally clamped at 600mv when r ocset is not connected, this preset threshold voltage may be very high to most of applications. hence, it is recommended to keep the r ocset always well-connected to protect the converter from over-current condition. where v boot-phase represents the voltage across the bootstrap capacitor. it is important to make sure that the controller can dissipate the switching loss and have enough room for safe operation when power mosfets are paralleled. inductor selection inductor plays an important role in step-down converters because the energy from the input power rail is stored in it and then released to the load. from the viewpoint of efficiency, the dc resistance (dcr) of inductor should be as small as possible to minimize the conduction loss. in addition, because inductor uses most of the board space, its size is also important. low profile inductors can save board space especially when the height has limitation. however, low dcr and low profile inductors are usually cost ineffective. additionally, larger inductance results in lower ripple current, which means lower power loss. however, the inductor current rising time increases with inductance value. this means the transient response will be slower. therefore, the inductor design is a trade-off between performance, size and cost. i ocset v cc r ocset lgate current sense and ocp comparator l phase oc control logic x1 v cc ugate boot phase v gd high-side mosfet v in d boot c boot mosfet driver r ugate
14 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v in pwm comparator dcr esr v out ea v ref r fb2 c out l out mosfet driver comp fb to load ramp q2 q1 c in + - + - z2 z1 figure 5. voltage mode control loop of buck converter output voltage of the converter is scaled by the divider resistors and then compared to the reference voltage, which is the regulation level seen by the controller. the error amplifier output voltage v comp is compared to the saw- tooth waveform from the oscillator to generate pwm signal. the output voltage is then regulated according to the duty cycle of the pwm signal. in out out min sw out_full load in vv v l, fki v where k is 0.2 to 0.4 ? ?? ?? input capacitor selection voltage rating and current rating are the key parameters in selecting input capacitor. generally, input capacitor has a voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. the input capacitor is used to supply the input rms current, which can be approximately calculated by the following equation : out out rms out in in vv ii 1 vv ?? ?? ?? ?? ?? the next step is to select proper capacitor for rms current rating. using more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank is a good design. besides, placing ceramic capacitor close to the drain of the high-side mosfet is helpful for reducing the input voltage ripple at heavy load. output capacitor selection the output capacitor and the inductor form a low-pass filter in the buck topology. the electrolytic capacitor is used for this application because it can provide large capacitance value. in steady state condition, the output capacitor supplies only ac ripple current to the load, which means the output capacitor must be able to handle the inductor ripple current. the ripple current flows into/out of the capacitor results in ripple voltage, which can be determined by the following equation : out_esr l vi x esr ??? in addition, the output voltage ripple is also influenced by the switching frequency and the capacitance value. out_c l out sw 1 v = i 8c f ??? ?? another parameter that has influence on the output voltage sag is the equivalent series inductance (esl). the rapid change in load current results in di/dt during transient. therefore, esl contributes to part of the voltage sag. using capacitors that have low esl can obtain better transient performance. generally, using several capacitors connected in parallel can have better transient performance than using single capacitor for the same total esr. unlike the electrolytic capacitor, the ceramic capacitor has relative low esr and can reduce the voltage deviation during load transient. however, the ceramic capacitor can only provide low capacitance value. therefore, using a mixed combination of electrolytic capacitor and ceramic capacitor can also have better transient performance. pwm feedback loop compensation in continuous conduction mode, the RT8130C operates with fixed frequency and uses voltage mode control for output voltage regulation. the ic utilizes voltage error amplifier with external compensation to provide flexibility in feedback loop compensator design. figure 5 shows the voltage mode control loop of a buck converter. the control loop consists of the modulator, power stage and the compensator. in general, inductance is designed so that the ripple current ranges between 20% to 40% of full load current. the inductance can be calculated by the following equation :
15 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. lc out out esr out 1 f 2l c 1 f 2c esr ? ? ? ?? ? ?? in order to obtain an accurate output voltage regulation and fast transient response, a compensator is necessary. depending on the inductor and output capacitor, different type of compensator can be used to finish the feedback loop compensation. by inserting a well designed compensator into the feedback loop, the closed loop control-to-output transfer function can be shaped to have adequate crossover frequency and sufficient phase margin. the design goals are: ? obtain high gain at low frequency for dc regulation accuracy ? obtain sufficient bandwidth for transient performance (generally, 1/10 to 1/5 switching frequency) ? obtain sufficient phase margin for stability (generally >45 ) figure 6 shows the type-iii compensator, which is composed of voltage error amplifier, impedance network z1 and z2. figure 6. type-iii compensator the type-iii compensator introduces three poles and two zeros to the system. the first pole is located in low frequency to increase the dc gain for voltage regulation accuracy and is usually referred to as the pole at zero. the location of rest of the two poles and two zeros can be determined as follows : ?? z1 z2 ss fb1 11 f, f 2rc 2 r2r c2 ?? ?? ?? ? ? ? p1 p2 sp s sp 11 f, f 2r2c2 cc 2r cc ? ? ?? ?? ?? ? ?? ?? ? ?? figure 7 shows the system bode plot. the close loop gain is the sum of modulation gain and the compensation gain. the modulation dc gain is determined by v in / v osc , where v osc is peak to peak voltage of the saw-tooth ramp. in general, f z1 is placed at half of f lc , and f z2 is placed at f lc to boost the large phase lag created by the double pole especially when esr is low. f p1 is typically placed at f esr to obtain a ? 20db/dec slope at crossover frequency. f p2 is placed at half of the switching frequency to increase the attenuation in high frequency. after calculating the compensation values, draw the system bode plot to check the crossover frequency and phase margin. due to the circuit parasitic components and the characteristic deviation in the inductor and output capacitors, further tuning of the compensation value to obtain the required crossover frequency and phase margin is necessary. + - v ref ea z2 z1 v out fb r s c2 r2 c s c p r fb1 r fb2 comp the system open loop gain has two poles at f lc and one zero at f esr . the frequency of f lc and f esr can be calculated by the following expressions : out comp ? v ? v figure 7. system bode plot 0 f lc f esr f z1 (db) freq.(log) modulation gain compensation gain close loop gain f z2 f p2 f p1 f cross
16 RT8130C www.richtek.com ds8130c-00 april 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations pcb layout plays an important role in high current, high frequency switching converter design. the general layout guide line is listed as follows. ? minimize the high-current loop as short as possible. the current transition between mosfets usually causes di/ dt voltage spike and thus the emi issue due to parasitic components on pcb trace and component lead. the pcb trace parasitic components cause not only excessive voltage spike, but also power loss. to reduce the pcb trace parasitic, place the high-side, low-side mosfets and the inductor with short current loop as possible. ? connect the controller and power mosfets with wide width and short length pcb traces. because the RT8130C has integrated high-current mosfet gate drivers, the pcb trace for mosfet driving should be sized to carry at least 2a peak current. ? for bootstrap circuit, place the bootstrap diode d boot close to the boot pin, and place the bootstrap capacitor c boot physically close to boot pin and phase pin with wide and short copper trace connection. ? place the ceramic capacitor close to the vcc pin for noise de-coupling. ? place all the function setting and compensation components as close to their associated pins as possible. this includes : ? place the compensation components close to the fb pin and comp pin to avoid noise pickup. voltage divider resistors connected to the fb pin should be placed close to the controller. ? place the ocp setting resistor r ocset close to the lgate pin. ? ? place the small-signal mosfet or bjt used for enable/ disable function close to the comp pin. ? place ceramic capacitor close to the drain of high-side mosfet to decrease the input voltage ripple. ? the output voltage feedback trace should be away from the switching node, power mosfets and inductor to avoid noise pickup. ? place the bulk capacitors close to the load. figure 8. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-10l 3x3 packages, the thermal resistance, ja , is 30.5c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (30.5 c/w) = 3.27w for wdfn-10l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w ) four-layers pcb
17 RT8130C ds8130c-00 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 9. pcb layout guide v in v out mosfet driver trace : wide and short enough copper area to carry load current. keep voltage feedback trace away from noisy node. place c out close to load. place c in close to mosfet. enough vias around mosfet lead to inner ground layer. place snubber close to low-side mosfet. 5v/12v place bootstrap circuit close to the boot pin. place r ocset close to the lgate pin. r ocset r pgood d boot c boot place disable mosfet close to the comp pin. to other circuit via inner layer via inner ground layer place noise decoupling mlcc close to the vcc pin. 9 8 7 1 2 3 4 5 10 6 gnd 11 boot phase gnd lgate ugate pgood nc fb vcc comp/en en load
18 RT8130C www.richtek.com ds8130c-00 april 2016 richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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